In modern RF communication systems a semiconductor-based transmit-receive switch is often the last/first component encountered by a transmitted/received signal before/after encountering an antenna. Figures of merit for signal quality of such a transmit-receive switch are switch linearity and spurious harmonic emission levels.
Many of the main advances in semiconductor-based transmit-receive switches have been with respect to isolation and insertion loss. Groups of FETs are arranged in the switch along with judiciously chosen resistors and capacitors to ensure low insertion loss along the signal path and high isolation from the off paths. One general approach utilizes, instead of a single FET switch along each alternative path, a group of FET switches in series. This general approach moreover does not simply turn the FETs on and off by utilizing only a voltage at the gate, but instead biases both the gate and the source/drain in a forward and reverse manner to turn the FETs full-on and full-off respectively.
An example of such a prior art approach, explained in Nakatsuka et al. (U.S. Pat. No. 7,199,635) is presented in FIG. 1A. A single pole double throw (SPDT) switch 100 is shown. One input/output pole terminal 101 (referred to as the pole) is coupled through a first FET group switch 120 to a first input/output terminal 102, and is connected through a second FET group switch 130 to a second input/output terminal 103. Each FET group switch 120, 130 has a group of FET transistors (for example the group of FET transistors 122 in the first FET group switch 120) connected in series with the signal path from the pole 101 to the corresponding first or second input/output terminal 102, 103. Each FET group switch 120, 130 also includes a group of source/drain resistors (for example source/drain resistors 124) coupled to the sources and/or drains of the FETs of the group switch, and coupled to one of a first and second biasing terminal 111, 112. Each FET group switch also includes a group of gate resistors (for example gate resistors 126 of FET group switch 120) coupled to the gates of the FETs of the group switch and to the other one of the first and second bias terminals 111,112.
Some early work on T/R Switches based on CMOS is described in: Feng-Jung Huang, Kenneth O, A 900-MHz T/R Switch with a 0.8-dB Insertion Loss Implemented in a 0.5-um CMOS Process, IEEE 2000 Custom Integrated Circuits Conference; Takahiro Ohnakado et al, 21.5 dBm Power-Handling 5 GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration with Depletion-Layer-Extended Transistor (DETs), 2003 Symposium on VLSI Circuits Digest of Technical Papers; and F.-J Huang and K. O., A 0.5 umCMOS T/R Switch for 900 MHz wireless applications, IEEE J. Solid-State Circuits, Vol. 36, pp. 486-492, March 2001.
The gates of the first FET group switch 120 and the source/drains of the second FET group switch 130 are biased by the first biasing terminal 111, while the gates of the second FET group switch 130 and the source/drains of the second FET group switch 130 are biased by the second biasing terminal 112.
To connect the pole 101 to the first input/output terminal 102, the first biasing terminal 111 is set to VHI (a high-level voltage), while the second biasing terminal 112 is set to VLO (a low-level voltage), such that the FETs of the first FET group switch 120 are fully on and the FETs of the second FET group switch 130 are biased with reverse polarity and hence fully off, within the reliability/breakdown limits of operation. To connect the pole 101 to the second input/output terminal 103, the second biasing terminal 112 is set to VHI, while the first biasing terminal 111 is set to VLO, such that the FETs of the second FET group switch 130 are fully on and the FETs of the first FET group switch 120 are biased with reverse polarity and hence fully off, within the reliability/breakdown limits of operation.
This configuration fully biases each FET group switch with an on or off polarity ensuring respectively low insertion loss and high isolation which are very important when dealing with high-power signal transmission. It can be seen from the circuit design that the bias applied to each FET group switch differs only in polarity. For further clarity, it should be understood that whenever a BJT, FET, MOSFET, MUGFET, FET group switch, or any other transistor switch is said to be biased with, or applied with biasing of, an “on polarity” or “forward polarity”, the voltages applied to the gate and the source/drains are such that the respective transistor switch is in an “on state”. It also should be understood that conversely, whenever a transistor switch is said to be biased with or having applied thereto biasing of an “off polarity” or “reverse polarity”, the voltage applied to the gate and source/drains are of a polarity reverse from that which would be applied to the gate and source/drains to put the transistor in an “on state”. This is to be distinguished from a biasing which achieves an “off state” in the transistor but which is of the same polarity as that (albeit much smaller in magnitude) which achieves the “on state”, or a biasing of zero which may achieve the “off state” but which has no polarity.
An example of a second prior art approach according to Nakatsuka et al. (U.S. Pat. No. 7,199,635) is depicted in FIG. 1B. A single pole double throw switch 150 including series and shunt FETs a shown. One input/output pole terminal 151 is coupled through a first FET group switch 160 to a first input/output terminal 152, and is connected through a second FET group switch 170 to a second input/output terminal 153. At a junction between the first input/output terminal 152 and the first FET group switch 160 is a connection coupled through a third FET group switch 180 and a blocking capacitor 182, to ground 184. At a junction between the second input/output terminal 153 and the second FET group switch 170 is a connection coupled through a fourth FET group switch 190, and a blocking capacitor 192 to ground 194. Each of the FETs of the first FET group switch 160 is connected in series between the first input/output terminal 152 and the pole 151 while each of the FETs of the second FET group switch 170 is connected in series between the second input/output terminal 153 and the pole 151. Since each of the first and second FET group switches 160, 170 are coupled between the pole and an input/output terminal, they are referred to as the series FET group switches. Each of the FETs in the third FET group switch 180 is connected in series between the first input/output terminal 152 and ground 184, while each of the FETs in the fourth FET group switch 190 is connected in series between the second input/output terminal 153 and ground 194. Since each of the third and fourth FET group switches 180, 190 coupled between an input/output terminal and ground, they are referred to as shunt FET group switches.
A first biasing terminal 154 is coupled to the gates of the first and fourth FET group switches 160, 190 and the source/drains of the second and third FET group switches 170, 180. A second biasing terminal 155 is coupled to the Gates of the second and third FET group switches 170, 180 and the source/drains of the first and fourth FET group switches 160, 190.
When the first biasing terminal 154 is VHI and the second biasing terminal 155 is VLO, the first and fourth FET group switches 160, 190 are biased to full on while the second and third group switches 170, 180 are biased with reverse polarity to full off. Consequently, the pole 151 is strongly coupled with the first input/output terminal 152 while being strongly isolated from the second input/output terminal 153, the first input/output terminal 152 is strongly isolated from ground 184 while the second input/output terminal 153 is strongly coupled, or shunted, to ground 194.
Conversely, when the first biasing terminal 154 is VLO and the second biasing terminal 155 is VHI, the second and third FET group switches 170, 180 have a strong inversion layer such that they are fully on while the first and fourth group switches 160, 190 are biased with a reverse polarity and are fully off. Consequently, the pole 151 is strongly coupled with the second input/output terminal 153 while being strongly isolated from the first input/output terminal 152, the first input/output terminal 152 is strongly coupled, or shunted, to ground 184 while the second input/output terminal 153 is strongly isolated from ground 194.
The prior art single pole double throw switch depicted in FIG. 1B achieves higher isolation than the prior art single pole double throw switch depicted in FIG. 1A by strongly coupling the input/output terminal which is not in use to ground.
Although the prior art approaches have achieved high isolation and low insertion loss many other performance factors and considerations for the transmit-receive switch have not been adequately addressed thereby.